Cypress Semiconductor /psoc63 /SMIF0 /DEVICE[0] /CTL

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Interpret as CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WR_EN)WR_EN 0 (CRYPTO_EN)CRYPTO_EN 0DATA_SEL 0 (ENABLED)ENABLED

Description

Control

Fields

WR_EN

Write enable: ‘0’: write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error. ‘1’: write transfers are allowed to this device.

CRYPTO_EN

Cryptography on read/write accesses: ‘0’: disabled. ‘1’: enabled.

DATA_SEL

Specifies the connection of the IP’s data lines (spi_data[0], …, spi_data[7]) to the device’s data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7): ‘0’: spi_data[0] = IO0, spi_data[1] = IO1, …, spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode. ‘1’: spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes. ‘2’: spi_data[4] = IO0, spi_data[5] = IO1, …, spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad SPI modes. In dual quad SPI mode, this value must be used for the second device. ‘3’: spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.

ENABLED

Device enable: ‘0’: Disabled. ‘1’: Enabled.

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